募集要項
- 仕事内容
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最大手ファンダリーのPhysical Design Manager & Engineer (ASIC/SoC Place & Route)Responsibilities:
*Perform the following:
- Chip/Block level floorplan,
- Clock tree synthesis,
- Place & Route,
- RC extraction,
- STA, timing closure,
- IR/EM analysis and fix,
- DRC/LVS/ERC analysis and fix,
- Tape-out sign off.
- Customer on-site support.
- 応募資格
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- 必須
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求める学歴：大学卒以上
Requirements:
*Education:
- Bachelor/Master’s degree in Electrical Engineering or Computer Science.
*5-15 years Netlist (or RTL)-GDS physical implementation experience.
*Language: Proficiency in English is basic requirement. Proficiency in Chinese is a plus.
*In depth knowledge of major EDA tools/design flows.
*Experience with TSMC N16 or below technology.
*Experience in block level implementation, chip integration and signoff.
*Experience in Perl/TCL language programming.
*Proven record in multi-million gate design production tapeouts.
*Experience in any of the following is a plus:
- FinFet Design
- TSMC N7 and below technology.
- Low-power implementation methodology.
- Advanced timing signoff methodology.
- Independently complete Netlist-GDS P&R, signoff task.
- 歓迎
- ・中国語が話せれば尚可
- フィットする人物像
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*Personal Attributes:
- Aggressive in learning and problem-solving.
- Good communication skill and a good team player.
- Strong project ownership and commitment.
- Self-motivated and can work independently.
- 雇用形態
- 正社員 ※試用期間3ヶ月
- 勤務地
- 神奈川県 横浜
- 年収・給与
- 年収：1000万円～1200万円
- 待遇・福利厚生
- 各種完備
- 休日休暇
- 週休2日（土日）、祝日休、夏休み、年末年始休
