設計・開発エンジニア(半導体)
【英語を活かす】シニアチップレット物理設計エンジニア/ Sr. Physical Design Engineer
の転職・求人情報はすでに掲載終了しております。(掲載期間11月11日~11月24日)
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掲載時の募集要項(掲載期間:2024/11/11 ~ 2024/11/24)
設計・開発エンジニア(半導体)
【英語を活かす】シニアチップレット物理設計エンジニア/ Sr. Physical Design Engineer
Global semiconductor company
外資系企業
管理職・マネジャー
英語力が必要
土日祝休み
募集要項
募集背景
-
A global semiconductor company is looking for a Senior Chiplet Physical Design Engineer. The selected candidate will be responsible for synthesis, place and route, and chip design integration, collaborating with experts worldwide. This is a hybrid setup role.
仕事内容
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A global semiconductor company is looking for a Senior Chiplet Physical Design Engineer.
Responsibilities:
* Perform synthesis and place and route using industry-standard tools for high-speed CPU core design
* Plan resources, schedule, and project PPA
* Develop strategies to achieve reproducible design convergence results
* Create and refine synthesis and PNR flow for the project team
* Perform all aspects of design flow, including logic synthesis, place and route, FEV, power, timing, quality checks, and design closure
* Develop and recommend better design methodologies to enable improved timing convergence
* Guide and mentor junior engineers
* Conduct PV convergence, including static timing and power analysis
* Perform chip physical design verification, including formal equivalence, timing, electrical rules, DRC/LVS, noise, and electro-migration checks
* Script in interpreted languages (minimum TCL, plus one other)
Requirements:
* Bachelor's degree or above in Electrical Engineering, Computer Engineering, or Computer Science
* More than 10 years of relevant industry experience
* Practical experience with integrated circuit design tools (Synopsys/Cadence)
* Proven experience with PV convergence, including static timing and power analysis
* Expertise in chip physical design verification, including formal equivalence, timing, electrical rules, DRC/LVS, noise, and electro-mitigation checks
* Hands-on experience with synthesis, block, and chip-level implementation using industry-standard PnR flows and tools
* Strong background in SoC/ASIC/GPU/CPU design flows on taped-out designs
* Scripting skills in Python and TCL
* Possess a valid authorisation to work in Japan
* Proficient in verbal and written English; fluent level Japanese is a plus
応募資格
-
- 必須
-
More than 10 years of relevant industry experience
- 歓迎
-
Practical experience with integrated circuit design tools (Synopsys/Cadence)
雇用形態
-
Permanent
勤務地
-
Tokyo
年収・給与
-
JPY10,000,000.00 - JPY15,000,000.00 per annum
休日休暇
-
完全週休2日制, 土日祝日休み, 有給休暇
会社概要
社名
-
Global semiconductor company
事業内容・会社の特長
-
A leading player in the seminconductor high-performance computing sector, this company specialises in developing innovative AI-driven solutions. With a global presence, it is at the forefront of revolutionising industries through cutting-edge technology and advanced hardware design.
Keywords:
チップ設計, 物理設計, 合成, ルート, CPU設計, シミュレーション, プロジェクト管理, 求人, 外資系
2126010/001
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