募集要項
- 募集背景
- A global semiconductor company is looking for a Senior Chiplet Physical Design Engineer. The selected candidate will be responsible for synthesis, place and route, and chip design integration, collaborating with experts worldwide. This is a hybrid setup role.
- 仕事内容
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A global semiconductor company is looking for a Senior Chiplet Physical Design Engineer.Responsibilities:
* Perform synthesis and place and route using industry-standard tools for high-speed CPU core design
* Plan resources, schedule, and project PPA
* Develop strategies to achieve reproducible design convergence results
* Create and refine synthesis and PNR flow for the project team
* Perform all aspects of design flow, including logic synthesis, place and route, FEV, power, timing, quality checks, and design closure
* Develop and recommend better design methodologies to enable improved timing convergence
* Guide and mentor junior engineers
* Conduct PV convergence, including static timing and power analysis
* Perform chip physical design verification, including formal equivalence, timing, electrical rules, DRC/LVS, noise, and electro-migration checks
* Script in interpreted languages (minimum TCL, plus one other)
Requirements:
* Bachelor's degree or above in Electrical Engineering, Computer Engineering, or Computer Science
* More than 10 years of relevant industry experience
* Practical experience with integrated circuit design tools (Synopsys/Cadence)
* Proven experience with PV convergence, including static timing and power analysis
* Expertise in chip physical design verification, including formal equivalence, timing, electrical rules, DRC/LVS, noise, and electro-mitigation checks
* Hands-on experience with synthesis, block, and chip-level implementation using industry-standard PnR flows and tools
* Strong background in SoC/ASIC/GPU/CPU design flows on taped-out designs
* Scripting skills in Python and TCL
* Possess a valid authorisation to work in Japan
* Proficient in verbal and written English; fluent level Japanese is a plus
- 応募資格
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- 必須
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More than 10 years of relevant industry experience
- 歓迎
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Practical experience with integrated circuit design tools (Synopsys/Cadence)
- 雇用形態
- Permanent
- 勤務地
- Tokyo
- 年収・給与
- JPY10,000,000.00 - JPY15,000,000.00 per annum
- 休日休暇
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完全週休2日制, 土日祝日休み, 有給休暇
