募集要項
- 仕事内容
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Location: Albany， NY： Santa Clara， CA： or Tokyo， Japan
Team: Enablement Team Technology Development
Job Description
We are seeking a highly motivated and experienced Senior DFT Engineer to join our Enablement Team supporting the development of advanced semiconductor process technologies at the 2nm node and beyond. You will lead the Design-for-Test (DFT) implementation of large-scale test chips that are critical for enabling and validating our next-generation manufacturing processes.
In this role， you will focus on scan insertion， ATPG， memory BIST， and other DFT methodologies， while also supporting yield analysis and EDA tool collaboration to improve design quality and test efficiency. You will work closely with RTL designers， physical design teams， process integration engineers， and EDA partners to ensure robust DFT infrastructure across our global sites.
Responsibilities
Define and implement DFT architectures for technology development test chips， focusing on scan，
- 応募資格
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- 必須
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【必須スキル・経験】
Minimum Qualifications
MS or PhD in Electrical Engineering， Computer Engineering， or a related field.
5+ years of experience in DFT development， preferably including advanced node designs or large-scale test chips.
Strong expertise in scan-based DFT， ATPG， compression， and memory BIST techniques.
Hands-on experience with commercial DFT tools (e.g.， Synopsys TestMax， Siemens Tessent， Cadence Modus).
Understanding of RTL-to-GDS flows and DFT timing considerations.
Practical experience in silicon bring-up， failure analysis， and yield improvement.
Excellent communication skills and the ability to work in a cross-site， cross-functional team.
【歓迎スキル・経験】
Preferred Qualifications
Experience with DFT implementation for sub-5nm technologies.
Experience with DFT
- 雇用形態
- 正社員
- 勤務地
- 北海道
- 年収・給与
- 400～1500万円
