募集要項
- 仕事内容
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Key Responsibilities
As a Test Chip Design Engineer， your responsibilities will include:
- Test Chip Physical Design and PPA Analysis:
- Backend (BE) Implementation and Related Flow Development: Drive the full backend implementation flow， from chip-level planning and PG (Power/Ground) network design to floorplan， place， CTS (Clock Tree Synthesis)， route， power analysis (PDNA sign-off)， and comprehensive physical verification.
- Design Methodology and EDA Tool Utility Development: Develop and enhance design methodologies and associated EDA tool utilities specifically for backend implementation. This includes creating solutions for challenges arising from new process technologies and developing utilities to support our customers effectively.
- Technology Benchmark: Conduct detailed technology benchmarking to thoroughly understand and evaluate the PPA characteristics of new process technologies.
- Collaborate closely with process development teams， circuit design teams， and ED
- 応募資格
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- 必須
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【必須条件】
Required Skills & Experience :
- Bachelor’s degree or higher in Electrical Engineering， Electronics Engineering， or a related field.
- 5+ years of hands-on experience in digital backend IC design， with a strong focus on physical design and sign-off.
- Proven expertise in the full physical design flow: floorplanning， power grid design， placement， clock tree synthesis (CTS)， routing， and physical verification (DRC/LVS/Antenna).
- Solid experience with power analysis (PDNA sign-off) and static timing analysis (STA).
- Proficiency with industry-standard EDA tools for physical design (e.g.， Cadence Innovus， Synopsys Fusion Compiler， PrimeTime， RedHawk， Calibre).
- Experience in scripting languages (e.g.， Tcl， Python， Perl) for design automation and flow development.
- Str
- 雇用形態
- 正社員
- 勤務地
- 北海道
- 年収・給与
- 400～1500万円
