募集要項
- 募集背景
- An international manufacturer of electronic components is searching for a Layout Engineer. The selected applicant will be responsible for creating standard cell and IO library memory and analogue IPs.
- 仕事内容
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An international manufacturer of electronic components is searching for a Layout Engineer.Responsibilities:
* Create memory IPs and test vehicles
* Improve RDR design guidelines
* Assess design rule impact on area and performance
* Define layout solutions to minimise RDR impact
Requirements:
* Bachelor's degree or above in electrical engineering or relevant engineering discipline
* 3+ years of professional experience
* Strong knowledge of SRAM, IO, and analogue layouts
* Japanese proficiency (communicative level English is a plus)
- 応募資格
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- 必須
- 3+ years of professional experience
- 歓迎
- 英語力必要。その他は詳細からご確認ください。
- 雇用形態
- Permanent
- 勤務地
- Kanagawa
- 年収・給与
- JPY8,000,000.00 - JPY11,000,000.00 per annum
- 休日休暇
- 完全週休2日制, 土日祝日休み, 有給休暇